1. Field of the Invention
The present invention relates generally to a system-on-a-chip-based scan chain linkage switch and, more particularly, to a test access mechanism (TAM) that facilitates the various dynamic tests by guaranteeing reconfiguration capability while minimizing the hardware overhead of the test access configuration of intellectual property cores embedded in a system-on-a-chip.
2. Description of the Related Art
As the degree of integration of a chip rapidly increases recently with the help of the development of semiconductor technology, a System-on-a-Chip (SoC) in which a system composed of cores, such as a processor and memory, is implemented in a single chip is widely used. The period of design is considerably reduced using reusable Intellectual Property (IP) cores, but a test and verification process causes a principal bottleneck in SoC design, so that various test technologies for the cores of the SoC have been developed.
In general, the important components of a test access configuration for an SoC composed of IP cores include a TAM and a test wrapper. The TAM includes a scan chain and a Built-In Self-Test (BIST) for inputting core internal test patterns. It is difficult to standardize the TAM.
A conventional Core Access Switch (CAS)-BUS, which was disclosed in the thesis “CAS-BUS: a scalable and reconfigurable test access mechanism for systems on a chip,” Design, Automation and Test in Europe Conference, Proceedings, pp. 141-145, 2000, by M. Benabdenebi, W. Maroufi and M. Marzouki, was proposed for test access to an SoC composed of heterogeneous cores. However, the structure of the CAS is complicated, so that the actual application of the CAS-BUS to a system chip incurs high costs.
FIG. 1 is an example of various test functions that can be performed by the conventional CAS-BUS. Referring to FIG. 1, one CAS is required for one core, an SoC test controller is used, and various test functions, such as core internal and external tests, a BIST and a hierarchical core test, are provided.
FIG. 2 is a configuration diagram showing the linkage of a CAS to an IP core surrounded by a P1500 wrapper. As shown in FIG. 2, the CAS is a switch that links P lines from N test bus terminals to scan chain input terminals and links P core scan chain output terminals to the test buses again. The linkage of N test bus terminals to P core scan chain input/output terminals for a corresponding core is completed by applying an instruction to the lowest input pin e0 of the N test bus terminals.
Such CAS-based TAM control technology is easy to reconfigure and is useful for performing a core internal test, a BIST and a core external test. However, the CAS-based TAM control technology is disadvantageous in that the structure of the CAS becomes complicated as the width of test buses and the number of core scan chains increase. The number of cases of selectively linking N test bus terminals to P scan chain input/output terminals in consideration of order is NPP (N Permutation P), which should be supported by a CAS configuration instruction, so that the design of the CAS becomes very complicated. In actual linkage cases, when N is six and P is three, the number of cases of linkage is 120, the length of an instruction is 7 bits, and the area of a CAS circuit is 280 gates. When N is eight and P is four, the number of cases of linkage is 1680, the length of an instruction is 11 bits, and the area of a CAS circuit is 4400 gates. As described above, it can be understood that the length of an instruction and the area of a CAS circuit rapidly increase.
Such CAS is problematic in that it is difficult for the CAS to be applied to an actual commercial Application-Specific Integrated Circuit (ASIC) in which the number of scan chains is several tens or more and the total number of scan cells is several hundreds of thousands.